Data processing circuit and fault mitigating method

A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural net...

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Bibliographic Details
Main Authors Wu, Kai-Chiang, Chen, Chien-Fa, Liu, Shu-Ming, Tang, Wen Li
Format Patent
LanguageEnglish
Published 07.05.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.
Bibliography:Application Number: US202217705415