Selective inhibit bitline voltage to cells with worse program disturb

A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line wheth...

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Bibliographic Details
Main Authors Lien, Yu-Chung, Kumar, Ravi, Islam, Sujjatul, Pitner, Xue
Format Patent
LanguageEnglish
Published 30.04.2024
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.
Bibliography:Application Number: US202217682280