Unified sequencer concurrency controller for a memory sub-system

An input/output (I/O) command referencing a memory device is identified. A power limit of the memory device is determined. A power level associated with executing the I/O command is estimated. Responsive to determining that the power level satisfies the power limit, the I/O command is executed.

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Bibliographic Details
Main Authors Zhu, Fangfang, Tai, Ying Y, Zhu, Jiangli
Format Patent
LanguageEnglish
Published 30.04.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An input/output (I/O) command referencing a memory device is identified. A power limit of the memory device is determined. A power level associated with executing the I/O command is estimated. Responsive to determining that the power level satisfies the power limit, the I/O command is executed.
Bibliography:Application Number: US202117463100