Timing error detection and correction circuit

An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit...

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Bibliographic Details
Main Authors Uytterhoeven, Roel Lieve P, Dehaene, Wim
Format Patent
LanguageEnglish
Published 30.04.2024
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.
Bibliography:Application Number: US202117335178