Semiconductor structure having high breakdown voltage etch-stop layer

The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the f...

Full description

Saved in:
Bibliographic Details
Main Authors Lan, Chin Kun, Liou, Joung-Wei
Format Patent
LanguageEnglish
Published 16.04.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.
Bibliography:Application Number: US202217875464