Semiconductor memory device and memory system including the same

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in res...

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Bibliographic Details
Main Authors Cho, Sungyong, Kim, Hyeran, Kim, Kiheung
Format Patent
LanguageEnglish
Published 09.04.2024
Subjects
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.
Bibliography:Application Number: US202217703049