Synchronisation for a multi-tile processing unit
A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that p...
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Main Authors | , , , , , , |
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Format | Patent |
Language | English |
Published |
12.03.2024
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Subjects | |
Online Access | Get full text |
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Summary: | A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit. |
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Bibliography: | Application Number: US202117446681 |