High voltage device with gate extensions

The present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate. The substrate is selectively etched to form a gate base recess within the substrate. The plurality of isolation structures are selectively etc...

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Bibliographic Details
Main Authors Chen, Jhih-Bin, Liu, Ming Chyi
Format Patent
LanguageEnglish
Published 20.02.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate. The substrate is selectively etched to form a gate base recess within the substrate. The plurality of isolation structures are selectively etched to form a plurality of gate extension trenches extending outward from the gate base recess;forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; andforming a source region and a drain region on opposing sides of the gate electrode.
Bibliography:Application Number: US202217734344