Encapsulated vertical interconnects for high-speed applications and methods of assembling same
A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
30.01.2024
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Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting. |
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Bibliography: | Application Number: US202117218384 |