Centrally logging and aggregating miscompares on chip during memory test

A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes gene...

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Bibliographic Details
Main Authors Kan, Senwen, Payne, Andrew, Gossett, Jeffrey W, Pluhta, Michael Joseph, Rodell, Jr., Richard A, Benjaminsson, Bjarni
Format Patent
LanguageEnglish
Published 09.01.2024
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Summary:A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes generating miscompare results responsive to performing the memory test on the one or more memory banks of the memory device. The method includes determining failure diagnostic information based on the miscompare results. The method includes generating an error packet comprising the failure diagnostic information and the miscompare results. The method includes placing the error packet in a queue of a plurality of error packets to generate a queued error packet.
Bibliography:Application Number: US202117524039