Polarization controlled transistor
A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the secon...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
19.12.2023
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Subjects | |
Online Access | Get full text |
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Summary: | A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction. |
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Bibliography: | Application Number: US202016920249 |