Non-volatile memory (NVM) cell structure to increase reliability

Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the se...

Full description

Saved in:
Bibliographic Details
Main Authors Ko, Chun-Yao, Chen, Shih-Hsien, Tsui, Felix Ying-Kit
Format Patent
LanguageEnglish
Published 12.12.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.
Bibliography:Application Number: US202217854068