Defect offset correction

A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within im...

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Bibliographic Details
Main Authors Hsueh, Ya-Hsun, Chuang, Sheng-Hsiang, Pai, Jiun-Rong, Liao, Chien-Ko, Kuo, Shou-Wen, Liu, Hsu-Shui
Format Patent
LanguageEnglish
Published 12.12.2023
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
Bibliography:Application Number: US202217881338