Write assist for a memory device and methods of forming the same

A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist...

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Bibliographic Details
Main Authors Singh, Sahil Preet, Chen, Yen-Huei, Liao, Hung-Jen
Format Patent
LanguageEnglish
Published 28.11.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
Bibliography:Application Number: US202217865453