Method to limit the time a semiconductor device operates above a maximum operating voltage

• Main Authors: Collura, Adam Benjamin, Cichanowski, Mark, Romain, Michael, Huott, William V, Buyuktosunoglu, Alper, Webel, Tobias, Jacobi, Christian, Saporito, Anthony, Cadigan, Jr., Michael Joseph, Owczarczyk, Pawel, Carey, Sean Michael, Payer, Stefan, Anderson, Karl Evan Smock, Logsdon, Paul Jacob, Shum, Chung-Lung K
• Format: Patent
• Language: English
• Published: 14.11.2023
• Subjects: CALCULATING; COMPUTING; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS; GENERATION; PHYSICS

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.