Systems and methods for semiconductor adaptive testing using inline defect part average testing
Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor...
Saved in:
Main Authors | , , , , , |
---|---|
Format | Patent |
Language | English |
Published |
24.10.2023
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process. |
---|---|
Bibliography: | Application Number: US202117333770 |