Via landing enhancement for memory device

A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode...

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Bibliographic Details
Main Authors Chuang, Harry-Hak-Lay, Hsieh, Chang-Jen, Wang, Hung Cho, Liao, Chun-Heng
Format Patent
LanguageEnglish
Published 10.10.2023
Subjects
ELECTRICITY
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Summary:A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.
Bibliography:Application Number: US202117319590