Universal data path architecture for different data array

A data path for memory addressable using an addressing scheme based on a minimum addressable unit, such as a byte, having a size (e.g. 8) which is a power of 2, is configured for transferring data between the memory array and a data interface using a transfer storage unit having N bits (e.g. 12), wh...

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Bibliographic Details
Main Author Hung, Shuo-Nan
Format Patent
LanguageEnglish
Published 10.10.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A data path for memory addressable using an addressing scheme based on a minimum addressable unit, such as a byte, having a size (e.g. 8) which is a power of 2, is configured for transferring data between the memory array and a data interface using a transfer storage unit having N bits (e.g. 12), where N is an integer that is not a power of 2. A page buffer and cache in the data path can be configured in unit arrays with N rows, and to transfer data in the transfer storage units from selected N cell columns.
Bibliography:Application Number: US202217667384