System and method for improving design performance through placement of functional and spare cells by leveraging LDE effect

• Main Authors: Chen, Wen-Hao, Chang, Jyun-Hao, Yu, Ming-Tao, Ku, Chun-Yao
• Format: Patent
• Language: English
• Published: 12.09.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design. According to some embodiments, conducting placement and optimization further includes: moving the at least one spare cells to locations to abut the at least one timing critical cells to form pattern-S for each of the at least one timing critical cells.