Method for fabricating a metal gate transistor with a stacked double sidewall spacer structure
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removin...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
29.08.2023
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Subjects | |
Online Access | Get full text |
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Summary: | A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL. |
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Bibliography: | Application Number: US202016985242 |