Protective liner layers in 3D memory structure

• Main Authors: Sun, Hung-Chang, Wu, Chen-Jun, Yang, Feng-Cheng, Yang, Tsu Ching, Lai, Sheng-Chih, Jiang, Yu-Wei, Lin, Chung-Te, Chiang, Kuo-Chang
• Format: Patent
• Language: English
• Published: 08.08.2023
• Subjects: ELECTRICITY

A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.