Integrated timing skew calibration with digital down conversion for time-interleaved analog-to-digital converter

• Main Authors: Powell, Scott R, Kao, Sean Wen, Ghazikhanian, Leo, Guan, Claire Huinan
• Format: Patent
• Language: English
• Published: 08.08.2023
• Subjects: BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRICITY

An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.