Dynamic inhibit voltage to reduce write power for random-access memory

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the mem...

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Bibliographic Details
Main Authors Lin, Zheng-Jun, Su, Chin-I, Chou, Chung-Cheng, Tseng, Pei-Ling
Format Patent
LanguageEnglish
Published 01.08.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
Bibliography:Application Number: US202117470849