Memory device for supporting command bus training mode and method of operating the same

There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, whi...

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Bibliographic Details
Main Authors Ha, Kyung-soo, Kim, Si-hong, Kim, Young-hun, Oh, Tae-young
Format Patent
LanguageEnglish
Published 01.08.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.
Bibliography:Application Number: US202117518888