Package structure and manufacturing method thereof

• Main Authors: Peng, Chia-Yu, Lin, Pu-Ju, Lau, John Hon-Shing, Ko, Cheng-Ta, Tseng, Tzyy-Jang, Yang, Kai-Ming, Kuo, Chi-Hai
• Format: Patent
• Language: English
• Published: 25.07.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.