NAND flash array defect real time detection

A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signa...

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Bibliographic Details
Main Authors Piccardi, Michele, Tripathi, Manan, Guo, Xiaojiang, Hoei, Jung Sheng
Format Patent
LanguageEnglish
Published 25.07.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.
Bibliography:Application Number: US202217874501