Enabling removal and reconstruction of flag operations in a processor

In one embodiment, a processor includes fetch logic to fetch instructions, decode logic to decode the fetched instructions, and execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed,...

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Bibliographic Details
Main Authors Gradstein, Amit, Weiner, Tomer, Ravid, Itai, Gerber, Alex, Rubanovich, Simon, Sperber, Zeev
Format Patent
LanguageEnglish
Published 25.07.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In one embodiment, a processor includes fetch logic to fetch instructions, decode logic to decode the fetched instructions, and execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer.
Bibliography:Application Number: US202117335284