Synchronizing dynamic link budgets with FPGA based simulation waveform state machines
A system for simulating lost data packets. The system includes a first hardware register storing data for fast factors. The fast factors include factors that are time independent with respect to particular data packets. A second hardware register stores slow factors. The slow factors include factors...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
20.06.2023
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Subjects | |
Online Access | Get full text |
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