Synchronizing dynamic link budgets with FPGA based simulation waveform state machines

• Main Authors: Jenkins, Stephen N, Thorup, Seth J, Kenney, Brent A, Morrey, Kyle R
• Format: Patent
• Language: English
• Published: 20.06.2023
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A system for simulating lost data packets. The system includes a first hardware register storing data for fast factors. The fast factors include factors that are time independent with respect to particular data packets. A second hardware register stores slow factors. The slow factors include factors that are time dependent on data packets. Synchronization hardware is coupled to the second hardware register and synchronizes the slow factors with specific data inputs based on dependencies on the data packets. A hardware adder is coupled to the first hardware register and the second hardware register to compute a link budget. The link budget is used in determine probability of loss of data packets. A hardware processor coupled to the hardware adder determines, based on the link budget, if a data packet should be dropped, and when the data packet should be dropped, drops the data packet for simulating a network physical layer.