Multiple independent on-chip interconnect

• Main Authors: Lahav, Sagi, Garg, Gaurav, Kolor, Sergio, Redshaw, Jonathan M, Vash, James, Kaushikkar, Harshavardhan, Fishwick, Steven, Zimet, Lior, Fukami, Shawn M, Tamari, Eran, Zemer, Tzach, Hammarlund, Per H, Hutsell, Steven R, Tota, Sergio V
• Format: Patent
• Language: English
• Published: 13.06.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.