Device architectures having engineered stresses

The present disclosure relates to a method that includes depositing a spalling layer onto a surface that includes a substrate, depositing a device comprising a III-V material onto the spalling layer, resulting in the forming of a stack, and dividing the stack substantially at a plane positioned with...

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Bibliographic Details
Main Author Steiner, Myles Aaron
Format Patent
LanguageEnglish
Published 23.05.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present disclosure relates to a method that includes depositing a spalling layer onto a surface that includes a substrate, depositing a device comprising a III-V material onto the spalling layer, resulting in the forming of a stack, and dividing the stack substantially at a plane positioned within the spalling layer to form a first portion that includes the substrate and a second portion that includes the PV device, where the spalling layer includes a first layer configured to provide a compressive stress and a second layer configured to provide a tensile stress, the first layer and the second layer form an interface, the dividing occurs as result of the interface, and the compressive stress and the tensile stress are strain-balanced so that a total strain within the spalling layer is approximately zero.
Bibliography:Application Number: US202117484578