Data tiering in heterogeneous memory system
A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memo...
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| Main Authors | , , , |
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| Format | Patent |
| Language | English |
| Published |
23.05.2023
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memory access address; classify each memory access address into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and allocate the first memory for frequently accessed data associated with the frequently accessed address and the second memory for normal data associated with the normal accessed address. |
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| AbstractList | A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memory access address; classify each memory access address into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and allocate the first memory for frequently accessed data associated with the frequently accessed address and the second memory for normal data associated with the normal accessed address. |
| Author | Kang, Myeong Joon Lim, Hyung Jin Kim, Jongryool Han, Miseon |
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| Snippet | A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory... |
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| Title | Data tiering in heterogeneous memory system |
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