Data tiering in heterogeneous memory system

A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memo...

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Bibliographic Details
Main Authors Kim, Jongryool, Lim, Hyung Jin, Han, Miseon, Kang, Myeong Joon
Format Patent
LanguageEnglish
Published 23.05.2023
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memory access address; classify each memory access address into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and allocate the first memory for frequently accessed data associated with the frequently accessed address and the second memory for normal data associated with the normal accessed address.
Bibliography:Application Number: US202117559962