Memory system architecture for multi-threaded processors

• Main Authors: Smith, Shaden, Pawlowski, Robert, More, Ankit, Jain, Samkit, Howard, Jason M, Cave, Vincent, Aananthakrishnan, Sriram, Krishnamurthy, Bharadwaj, Fryman, Joshua B, Zhong, Tina C, Pitchaimoorthy, Sowmya
• Format: Patent
• Language: English
• Published: 18.04.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.