Complementary clock gate and low power flip-flop circuit including same

A complementary clock gate, includes a NOR gate configured to receive a data signal D and a signal QI; a first P-type transistor gated by an output value of the NOR gate; and a NAND gate, connected in series to the first P-type transistor, configured to receive a clock signal CK and an inverted data...

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Bibliographic Details
Main Authors Shin, Gi Cheol, Lee, Yoon Myung
Format Patent
LanguageEnglish
Published 04.04.2023
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Online AccessGet full text

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Summary:A complementary clock gate, includes a NOR gate configured to receive a data signal D and a signal QI; a first P-type transistor gated by an output value of the NOR gate; and a NAND gate, connected in series to the first P-type transistor, configured to receive a clock signal CK and an inverted data signal DN, and output an inverted clock signal CKB.
Bibliography:Application Number: US202117496941