High-efficiency packaged chip structure and electronic device including the same

A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the botto...

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Bibliographic Details
Main Authors Chang, Wei-Chan, Hsieh, Cheng-Yi, Wu, Chun-Yi, Yu, Hsiu-Mei, Lin, Chang-Sheng
Format Patent
LanguageEnglish
Published 21.02.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.
Bibliography:Application Number: US202017095710