Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation

A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is...

Full description

Saved in:
Bibliographic Details
Main Authors Pipia, Francesco Maria, Venegoni, Ivan, Votta, Annamaria, Milanesi, Francesca, Colpani, Paolo, Sciarrillo, Samuele
Format Patent
LanguageEnglish
Published 21.02.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is formed in the hole. A barrier layer is formed in the hole and extends into the hole. A first coating layer covers a top and sides of a redistribution region of the conductive region and a second coating layer covers is formed covering the first coating layer. A capillary opening is formed extending into the first and second coating layers to the barrier layer. A cavity is formed between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure by passing an aqueous solution through the capillary opening.
Bibliography:Application Number: US202017000165