Voltage adjust circuit and operation method thereof

The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors...

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Bibliographic Details
Main Authors Chen, Yi-Jan, Chen, Chung-Hung, Jaw, Boy-Yiing, Li, Hsu-Chi, Chuang, Chin-Tang, Lu, Yi-Chen
Format Patent
LanguageEnglish
Published 17.01.2023
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.
Bibliography:Application Number: US202117516730