Systems and methods to reduce the impact of short bits in phase change memory arrays

A memory device includes a memory array comprising a plurality of memory elements and a memory controller coupled to the memory array. The memory controller when in operation receives an indication of a defect in the memory array determines a first location of the defect when the defect is affecting...

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Bibliographic Details
Main Authors Zhao, Peng, Ciocchini, Nicola
Format Patent
LanguageEnglish
Published 17.01.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device includes a memory array comprising a plurality of memory elements and a memory controller coupled to the memory array. The memory controller when in operation receives an indication of a defect in the memory array determines a first location of the defect when the defect is affecting only one memory element of the plurality of memory elements, determines a second location of the defect when the defect is affecting two or more memory elements of the plurality of memory elements, and performs a blown operation on a defective memory element at the second location when the defect is affecting two or more memory elements of the plurality of memory elements.
Bibliography:Application Number: US202117221108