3D cross-bar nonvolatile memory

Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The metho...

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Bibliographic Details
Main Authors Diaz, Carlos H, Guo, Ta-Pen, Colinge, Jean-Pierre
Format Patent
LanguageEnglish
Published 20.12.2022
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES
NANOTECHNOLOGY
PERFORMING OPERATIONS
PHYSICS
SEMICONDUCTOR DEVICES
SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES
STATIC STORES
TRANSPORTING
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Summary:Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.
Bibliography:Application Number: US202016921606