Systems, apparatuses, and methods for fused multiply add

• Main Authors: Gradstein, Amit, Ould-Ahmed-Vall, Elmoustapha, Majcher, Piotr, Girkar, Milind B, Charney, Mark J, Valentine, Robert, Ryvchin, Galina, Corbal, Jesus, Rubanovich, Simon, Sperber, Zeev
• Format: Patent
• Language: English
• Published: 13.12.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.