Systems and methods of resilient clock synchronization in presence of faults

The present disclosure provides an analytical framework to investigate judicious topology reweighting of radio networks of clocks, when distributed time transfer and synchronization are based on physical layers and subject to the presence of false timing signals. Protagonist clocks exchange timing i...

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Bibliographic Details
Main Author Pham, Khanh
Format Patent
LanguageEnglish
Published 22.11.2022
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
WIRELESS COMMUNICATIONS NETWORKS
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Summary:The present disclosure provides an analytical framework to investigate judicious topology reweighting of radio networks of clocks, when distributed time transfer and synchronization are based on physical layers and subject to the presence of false timing signals. Protagonist clocks exchange timing information pairwise, which is modeled as clocks tending to follow the majority of their neighbors. Antagonist clocks inject false timing signals, thereby, influencing the timing synchronization of (some of) the other protagonist clocks they meet. A class of pursuit-evasion graphical games subject to complete state observations and exploitation of phase noise disturbances, is proposed in designing clock steering protocols for resilient time metrologies that will be immune to erroneous timing signals injected into remote time dissemination networks.
Bibliography:Application Number: US202117185110