Data compression and encryption based on translation lookaside buffer evictions

A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identif...

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Bibliographic Details
Main Authors Poremba, Matthew R, Kotra, Jagadish B, Loh, Gabriel H
Format Patent
LanguageEnglish
Published 22.11.2022
Subjects
ADVERTISING
CALCULATING
CODING OR CIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHERPURPOSES INVOLVING THE NEED FOR SECRECY
COMPUTING
COUNTING
CRYPTOGRAPHY
DISPLAY
EDUCATION
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
SEALS
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Summary:A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.
Bibliography:Application Number: US202017135325