System physical address size aware cache memory

In certain aspects, a tag memory comprises a plurality of non-configurable tag columns configured to be powered on during a normal operation; and a plurality of configurable tag columns, wherein a first portion of the plurality of configurable tag columns is configured to be powered off during the n...

Full description

Saved in:
Bibliographic Details
Main Authors Turaga, Srinivas, Rangarajan, Bharat Kumar
Format Patent
LanguageEnglish
Published 22.11.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:In certain aspects, a tag memory comprises a plurality of non-configurable tag columns configured to be powered on during a normal operation; and a plurality of configurable tag columns, wherein a first portion of the plurality of configurable tag columns is configured to be powered off during the normal operation and a second portion of the plurality of configurable tag columns is configured to be powered on during the normal operation.
Bibliography:Application Number: US202016799936