Computation-in-memory in three-dimensional memory device

Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a 3D NAND memory array and an on-die data processing circuit coupled to the 3D NAND memory array on a same chip. The on-die data processing circuit is configured to receive, from an input/output (I/O) interfac...

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Bibliographic Details
Main Authors Han, Kun, Xia, Zhongyi, Yang, Shengwei
Format Patent
LanguageEnglish
Published 04.10.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a 3D NAND memory array and an on-die data processing circuit coupled to the 3D NAND memory array on a same chip. The on-die data processing circuit is configured to receive, from an input/output (I/O) interface, control instructions for performing operations on data stored in the 3D NAND memory array. The on-die data processing circuit is also configured to retrieve the data from the 3D NAND memory array based on the control instructions and perform the operations on the retrieved data. Moreover, the on-die data processing circuit is configured to return a result of the operations to the I/O interface.
Bibliography:Application Number: US201916542272