Four D device process and structure

• Main Authors: Haensch, Wilfried, Yu, Roy R
• Format: Patent
• Language: English
• Published: 04.10.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; LAYERED PRODUCTS; LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM; PERFORMING OPERATIONS; SEMICONDUCTOR DEVICES; TRANSPORTING

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory.