Epitaxial semiconductor liner for enhancing uniformity of a charged layer in a deep trench and methods of forming the same

Photodetectors, transistors, and metal interconnect structures may be formed on a front side of the semiconductor substrate. A trench is formed through a backside surface of the semiconductor substrate toward the front side by an anisotropic etch process, which provides a vertical or tapered surface...

Full description

Saved in:
Bibliographic Details
Main Authors Cheng, Yu-Hung, Tu, Yeur-Luen, Lee, Ru-Liang
Format Patent
LanguageEnglish
Published 02.08.2022
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:Photodetectors, transistors, and metal interconnect structures may be formed on a front side of the semiconductor substrate. A trench is formed through a backside surface of the semiconductor substrate toward the front side by an anisotropic etch process, which provides a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm. A single crystalline semiconductor liner is deposited by performing an epitaxial growth process at a growth temperature less than 500 degrees Celsius on the vertical or tapered surface of the trench. A physically exposed side surface of the single crystalline semiconductor liner may have a second root-mean-square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner having a uniform thickness may be formed on the physically exposed side surface to provide a uniform negatively charged film, which may be advantageously used to reduce dark current and white pixels.
Bibliography:Application Number: US202016901036