Stacked-gate transistors

The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a sup...

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Bibliographic Details
Main Authors Greene, Brian J, Chu, Tao, Liu, Bingwu, Li, Wenjun
Format Patent
LanguageEnglish
Published 02.08.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.
Bibliography:Application Number: US201916503982