Pre-discharging based flip-flop with a negative setup time

• Main Authors: Ghosh, Abhishek, Roy, Arani, Bhat, Aroma, Goyal, Mitesh, Rakheeb, Abdur
• Format: Patent
• Language: English
• Published: 14.06.2022
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; PULSE TECHNIQUE; TESTING

A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.