Indicating latency associated with a memory request in a system

Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface control...

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Bibliographic Details
Main Authors Gans, Dean D, Hasbun, Robert Nasry, Daruwalla, Sharookh
Format Patent
LanguageEnglish
Published 07.06.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.
Bibliography:Application Number: US202016886109